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16-bit, 400 msps d/a converter AD9726 rev. a in for m a t i o n f u r n is h e d b y an al o g d e vice s is b e li ev e d to b e accu ra te a n d reli abl e . h o w e v e r , n o r e sp o n sibi lit y is as s u m e d by an al o g d e vices fo r i t s u s e , n o r fo r a n y i n fr i n g e m e nts of pate n t s or ot h e r r i g h ts o f th ir d par t ies th a t m a y r e su l t f r o m i t s use . s p e c i f ica t io n s su bj e c t t o c h an g e w i th o u t n o ti c e . n o l i c e n s e i s g r an t e d b y imp l ic a t io n o r o t h e r w i s e un d e r an y pa t e n t o r pa t e n t r i g h t s o f a n a l o g d e v i c e s . t r adem ar ks and r e g i st e r ed tr ad ema r ks ar e the p r o p er t y of the i r r e sp e c t i v e o w ne rs . o n e t e chnology way, p . o. b o x 91 06, nor w ood , ma 020 62- 910 6, u. s . a. t e l: 781. 329. 4 700 w w w . analog .c om fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures d y namic per f o rmanc e sfdr 78 db c @ f out = 20 mh z imd 8 2 db c @ f out = 70 mhz a c lr 76 db c @ f out = 70 mh z nsd C16 0 db /hz @ f out = 7 0 mhz p r ecision c a libr a t ed l i nearit y dnl 0.5 lsb @ + 25 c in l 1.0 lsb @ +25c thd C95 db @ f out = 1 mh z l vds inputs with int e rnal 100 ? t e rmina tions a u t o ma tic da t a /clock timing synchr oniza t ion single da ta r a te o r do uble da t a r a te c a pable d i ff er entia l cur r ent outputs in t e rnal pr ecision r e f e r e nc e o p er a t es on 2.5 v and 3.3 v s u p p lies ex t e nded industrial t e mpe r a t ur e r a nge t h ermall y enh a nc ed , 80- lead , lead -fr ee t q fp _ep pack age applic a t io ns instrumen t a t ion t e st eq uipment w a v e f o rm s y n t hesis c o mmunic a tions sy st ems func ti on a l bl ock di a g r a m internal reference calibration memory lvds output driver data s y nchronization lv ds inp u t data cap ture spi csb sdio sdo reset i outa i outb refio fsadj sclk clk+ clk? dclk_out+ dclk_out? db[15]+ db[15]? db[0]+ db[0] ? dclk_in+ dclk_in? c l oc k d i s tr ib u t ion and co n t ro l 16- bi t dac 04540-001 figure 1. . gener a l description the AD9726 is a 16-b i t dig i tal-to-a nalog co n v er t e r (d a c ) t h a t of f e r s l e a d i n g e d ge p e r f or m a nc e a t c o n v e r s i on r a te s up to 400 ms ps. th e de vice us es lo w v o l t a g e dif f er en tial sig n alin g (l vds) in p u ts and in c l udes in t e r n al 100 ? t e r m ina t ion s . th e a n a l o g o u t p ut c a n b e sin g l e -e nde d o r d i f f er en t i a l c u r r en t. an in t e r n a l p r e c isio n r e fer e n c e is i n cl ud e d . the AD9726 als o f e a t ur es syn c hr o n iza t io n log i c t o m o ni t o r an d o p ti m i z e s th e ti m i n g be t w ee n i n co m i n g d a ta a n d th e sa m p l e c l oc k . this r e d u ces sy s t em co m p lexi ty a n d sim p lif i es timin g r e q u ir e- m e n t s. an l v d s c l oc k o u t p u t is als o a v a i la b l e t o dr i v e a n e x t e rnal da ta p u m p i n ei th e r sin g le d a ta ra t e (s d r ) o r do u b le d a ta ra t e ( ddr ) mo d e . al l de v i ce op era t io n is f u l l y p r og ra mma b l e using t h e f l exib le s e r i al p o r t in t e r f ace (s p i ). the AD9726 is als o f u l l y f u n c tio n al in i t s de fa u l t st a t e fo r a p plica t ion s w i t h o u t a con t r o l l er . produc t highlight s 1. a uniq ue co m b i n a t io n o f p r e c isi o n a nd p e r f o r ma n c e mak e s t h e ad9 726 eq ual l y s u i t ed t o a p p l ica t ion s wi t h deman d in g f r e q uen c y do ma i n o r dema nd in g t i m e do ma i n r e q u ir emen t s . 2. n o n v ol a t i l e f a c t or y c a l i b r a t ion assu re s a h i g h ly l i ne ar t r ans f e r f u nc t i on . in te r n a l l o g i c of f e r s on d e m a n d s e l f - ca l i b r a t io n fo r li n e a r i t y e v en a t ex tende d op er a t in g t e m p era t ur es. 3. propr i e t ar y arch i t e c t u re m i n i m i z e s d a t a d e p e nd e n t , dis c r e te mix i n g sp urs a nd o f fers en han c e d d y namic p e r f o r ma n c e o v er a wide ra n g e o f o u t p u t f r e q ue n c ies. h i g h i n p u t da t a ra t e s cr e a te a v e r y hig h f r e q uenc y syn t h e sis ban d wid t h. 4. t h e full y a u t o ma ti c, tra n s p a r e n t syn c h r o n iz e r m a i n ta i n s o p t i m i ze d t i mi n g b e twe e n clo c k an d d a t a in r e a l t i m e and of f e r s p r o g r a mm abl e c o n t ro l opt i ons f o r a d d e d f l e x ibi l it y . 5. f u ll -s cal e o u t p u t c u rr en t is ext e r n al r e s i s t o r p r og ra mm a b le .
AD9726 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 4 digital signal specifications ........................................................ 5 timing specifications .................................................................. 5 timing diagrams .......................................................................... 6 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 ter mi nolo g y .................................................................................... 10 typical performance characteristics ........................................... 11 serial port interface ........................................................................ 13 theory of operation ...................................................................... 15 dac clock and data clock output ........................................ 15 data clock input ........................................................................ 15 data synchronization circuitry ............................................... 16 analog output ............................................................................ 16 internal reference and full-scale output .............................. 16 reset ............................................................................................. 17 serial port interface ................................................................... 17 spi pin description .................................................................... 18 calibration ................................................................................... 18 sync logic operation and programming ............................... 20 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 11/05rev. 0 to rev. a changes to features.......................................................................... 1 changes to table 3 and table 4....................................................... 5 changes to the terminology section........................................... 10 changes to the driving the dac clock inputs section............ 15 changes to the reset and serial port interface sections ........... 17 updated outline dimensions ....................................................... 22 changes to the ordering guide.................................................... 22 7/05revision 0: initial version
AD9726 rev. a | page 3 of 24 specifications dc specifications dbvdd = avdd1 = avdd2 = 3.3 v, dvdd = clkvdd = advdd = acvdd = 2.5 v, i out-fs = 20 ma, internal reference, t min to t max , unless otherwise specified. table 1. parameter min typ max unit accuracy 1 dnl 0.5 1.0 lsb inl 1.0 2.5 lsb offset error 0.003 % fs gain error 0.003 % fs analog output full-scale current 20 ma compliance voltage 1 v output impedance 10 m? internal reference output voltage 1.18 1.22 1.27 v output current 2 1 a external reference input voltage 1.2 v input resistance 10 m? small signal bandwidth 200 khz temperature coefficients gain drift 10 ppm of fs/oc offset drift 10 ppm of fs/oc reference drift 30 ppm/oc power supplies 3 avdd1, avdd2 voltage range 3.13 3.47 v supply current (i avdd1 + i avdd2 ) 52 60 ma advdd, acvdd voltage range 2.37 2.63 v supply current (i acvdd + i advdd ) 16 18 ma clkvdd voltage range 2.37 2.63 v supply current (i clkvdd ) 45 50 ma dvdd voltage range 2.37 2.63 v supply current (i dvdd ) 80 90 ma dbvdd voltage range 3.13 3.47 v supply current (i dbvdd ) 16 18 ma power dissipation (p diss ) 575 mw sleep mode 465 mw power-down mode 10 mw operating temperature range C40 +85 c 1 t amb = 25c. 2 use buffer amplifier to drive external load. 3 supply currents and power diss ipation measured in sdr with f dac = 400 mhz and f out = 1 mhz.
AD9726 rev. a | page 4 of 24 ac specifications dbvdd = avdd1 = avdd2 = 3.3 v, dvdd = clkvdd = advdd = acvdd = 2.5 v, i out-fs = 20 ma, internal reference, t min to t max , unless otherwise specified. table 2. parameter min typ max unit total harmonic distortion (thd) f dac = 400 mhz, f out = 1 mhz, 0 dbfs C95 db spurious-free dynamic range (sfdr) f dac = 400 mhz, 0 dbfs f out = 20 mhz 78 dbc f out = 70 mhz 68 dbc f out = 140 mhz 62 dbc f dac = 400 mhz, C3 dbfs f out = 20 mhz 80 dbc f out = 70 mhz 70 dbc f out = 140 mhz 62 dbc f dac = 200 mhz, 0 dbfs f out = 20 mhz 84 dbc f out = 70 mhz 62 dbc f dac = 200 mhz, C3 dbfs f out = 20 mhz 82 dbc f out = 70 mhz 68 dbc two-tone intermodulation distortion (imd) f dac = 400 mhz, 0 dbfs f out1 = 20 mhz, f out2 = 21 mhz 86 dbc f out1 = 70 mhz, f out2 = 71 mhz 82 dbc f out1 = 140 mhz, f out2 = 141 mhz 74 dbc adjacent channel leakage ratio (aclr) f data = 245.76 msps, f carrier = 70 mhz, 1-carrier wcdma 76 dbc f data = 245.76 msps, f carrier = 70 mhz, 2-carrier wcdma 70 dbc f data = 245.76 msps, f carrier1 = 70 mhz, 4-carrier wcdma 66 dbc f data = 245.76 msps, f carrier1 = 70 mhz, 8-carrier wcdma 62 dbc noise spectral density (nsd) f dac = 400 mhz, f out = 70 mhz, 0 dbfs C160 dbm/hz f dac = 400 mhz, f out = 70 mhz, C3 dbfs C163 dbm/hz f dac = 400 mhz, f out = 70 mhz, C6 dbfs C165 dbm/hz update rate 0 400 msps
AD9726 rev. a | page 5 of 24 digital signal specifications dbvdd = avdd1 = avdd2 = 3.3 v, dvdd = clkvdd = advdd = acvdd = 2.5 v, i out-fs = 20 ma, internal reference, t min to t max , unless otherwise specified. table 3. parameter min typ max unit dac clock inputs (clk+/C) differential voltage 0.5 1.0 v common-mode voltage 1.0 1.25 v lvds inputs (db[15:0]+/C, dclk_in+/C) input voltage range 825 1575 mv differential threshold voltage 100 mv differential input impedance 100 ? lvds output (dclk_out+/C) differential output voltage 1 250 400 mv offset voltage 1.0 1.2 v short-circuit output current 20 ma cmos inputs (csb, sclk, sdio, reset) logic 0 voltage 0.5 v logic 1 voltage 2.5 v input current 1 na cmos outputs (sdo, sdio) logic 0 voltage 0.5 v logic 1 voltage 3.0 v short-circuit output current 10 ma control inputs (spi_dis, sdr_en) logic 0 voltage 0.5 v logic 1 voltage 2.0 v input current 1 na 1 with 100 ? external load. timing specifications dbvdd = avdd1 = avdd2 = 3.3 v, dvdd = clkvdd = advdd = acvdd = 2.5 v, i out-fs = 20 ma, internal reference, t min to t max , unless otherwise specified. table 4. parameter min typ max unit lvds data bus ddr dclk_out+/C propagation delay (t dcpd-ddr ) 2000 ps ddr db[15:0]+/C set-up time (t dsu-ddr ) C100 ps ddr db[15:0]+/C hold time (t dh-ddr ) 500 ps sdr dclk_out+/C propagation delay (t dcpd-sdr ) 300 ps sdr db[15:0]+/C set-up time (t dsu-sdr ) C100 ps sdr db[15:0]+/C hold time (t dh-sdr ) 500 ps serial port interface sclk frequency (f sclk ) 15 mhz sclk rise/fall time 1 ms sclk pulse width high (t cpwh ) 30 ns sclk pulse width low (t cpwl ) 30 ns sclk set-up time (t csu ) 30 ns sdio set-up time (t dsu ) 30 ns sdio hold time (t dh ) 0 ns sdio/sdo valid time (t dv ) 30 ns reset pulse width 1.5 ns
AD9726 r e v. a | pa ge 6 o f 2 4 timing diagrams dac clock dataclock outpu t dataclock input data bus t dcpd-ddr t dsu-ddr t dh-ddr 04540-002 figure 2. ddr t i ming diagr a m dac clock dataclock outpu t dataclock input data bus t dcpd-sdr t dsu-sdr t dh-sdr 04540-003 figure 3. sdr t i m i n g di agra m csb sclk s dio (sd0) t cpwh t dsu t dh t cpwl 04540- 004 sclk set-up time sdio set-up time sdio hold time sdio (sd0) valid time sclk pulse width high/low time t csu t dv figure 4. spi ti m i n g di agra m
AD9726 r e v. a | pa ge 7 o f 2 4 absolute maximum ra tings table 5. param e ter with re spect to rating dbvd d, av dd 1, avd d 2 dbgn d, agn d 1, agnd2 C0.3 v to 3.6 v d v dd , clkvdd , ac vdd, a d v dd d g n d , clkgnd , acgnd, a d gn d C0.3 v to 2.8 v dbgn d, agn d 1, agnd2 dbgn d, agn d 1, agnd2 C0.3 v to +0.3 v d g n d , clkgnd , acgnd, a d gn d d g n d , clkgnd , acgnd, a d gn d C0.3 v to +0.3 v refio, fsda j agnd 1 C0.3 v to av dd 1 + 0.3 v iouta, iou t b agnd1 C1.0 v to av dd1 + 0.3 v clk+ , clkC clkgnd C0.3 v to clkvdd + 0.3 v db[15:0] +/C, dc lk_in + /C, dclk_o ut+/C dbgn d ?0. 3 v to dbvd d + 0. 3 v csb, sclk, sdio, sdo, rese t, rex t dbgn d C0. 3 v to d b vd d + 0.3 v sdr_en, spi _ di s adgn d C0.3 v to adv dd + 0.3 v s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . thermal resistance ther mal i m p e da n c e can b e lo wer e d t o 23c/ w b y s o lder in g t h e e x posed pa c k a g e pa d t o a n e x t e rn al h e a t s i nk ( f o r e x a m p l e , th e i n te r n a l p c b co pp e r g r ou nd pl a n e ) . h o we ver , t h i s is not ne c e ss a r y fo r t h e p o w e r dis s i p a t ion an d op era t i n g t e m p er a t ur e ra n g e o f th e AD9726. table 6. therm a l resistance p a ck age t y pe ja unit 80-l e ad t q fp_e p p a ck age , ther mally enhanc ed 32 c/w esd caution esd (elec t r o sta t ic dischar g e) se nsitiv e devi c e . e l ec tr osta tic charges as high as 4 000 v r e adily accumula te on the human body and t e st eq uipmen t and can dischar g e with out det e c t ion. although this pr oduc t f e a tur es pr oprietar y esd pr ot ec tion cir c uitr y , permanen t dama ge may oc cur on dev i c e s sub j ec ted to high ener gy elec tr o s ta tic dischar g es . ther ef or e , p r o p er esd pr ecaution s ar e r e c o mme nded to a v oid per f or manc e degr ada - tion or los s of func tional it y .
AD9726 r e v. a | pa ge 8 o f 2 4 pin conf igura t ion and fu nction descriptions 04540-005 2 rext 3 clkvdd 4 clkgnd 7 clkgnd 6 clk ? 5 clk+ 1 clkvdd 8 dgnd 9 dvdd 10 db15+ 12 db14+ 13 db14? 14 db13+ 15 db13? 16 db12+ 17 db12? 18 db11+ 19 db11? 20 dbvdd 11 db15? 59 58 57 54 55 56 60 53 52 refio reset csb sdo (syncalrm) sdio sclk (syncupd) fsadj dgnd dvdd 51 db0? 49 db1? 48 db1+ 47 db2? 46 db2+ 45 db3? 44 db3+ 43 db4? 42 db4+ dbgnd 41 50 db0+ pin 1 21 dbgnd 22 d b 10+ 23 db1 0? 24 db9 + 25 db9 ? 26 db8 + 27 db8 ? 28 dclk_ out+ 29 dclk_ out? 30 dbv dd 31 dbgnd 32 dclk_ in+ 33 dclk_ in? 34 db7 + 35 db7 ? 36 db6 + 37 db6 ? 38 db5 + 39 db5 ? 40 dbv dd 80 spi_d is 79 adv dd 78 adgnd 77 acv dd 76 acgnd 75 av dd2 74 agnd2 73 av dd1 72 agnd1 71 iouta 70 ioutb 69 agnd1 68 av dd1 67 agnd2 66 av dd2 65 acgnd 64 acv dd 63 adgnd 62 adv dd 61 s dr_ e n AD9726 top view (not to scale) figure 5. pin c o nfiguration ta ble 7. pi n f u nct i on d e s c ri pt i o ns pi n n o . m n e m o n i c d e s c r i p t i o n 1 c l k v d d clock supply v o l t a g e 2 rex t sets da ta clock o utput driv e 1 3 c l k v d d clock supply v o l t a g e 4 clk g nd clock supply c o mmon 5 clk+ d a c clock i n put t r ue 6 clk? d a c clock i n put c o mple men t 7 clk g nd clock supply c o mmon 8 dgnd dig i tal supply c o mmon 9 d v d d dig i tal supply v o l t a g e 10 db15+ da ta bit 15 t r ue 11 db15? da ta bit 15 c o m p leme n t 12 db14+ da ta bit 14 t r ue 13 db14? da ta bit 14 c o m p leme n t 14 db13+ da ta bit 13 t r ue 15 db13? da ta bit 13 c o m p leme n t 16 db12+ da ta bit 12 t r ue 17 db12? da ta bit 12 c o m p leme n t 18 db11+ da ta bit 11 t r ue 19 db11? da ta bit 11 c o m p leme n t 20 dbvdd da ta bus supply v o ltage 21 dbgnd da ta bus supply c o mmon pi n n o . m n e m o n i c d e s c r i p t i o n 22 db10+ da ta bit 10 t r ue 23 db10? da ta bit 10 c o m p leme n t 24 db9+ da ta bit 9 t r ue 25 db9? da ta bit 9 c o mplemen t 26 db8+ da ta bit 8 t r ue 27 db8? da ta bit 8 c o mplemen t 28 dclk_out+ da ta clock o utput t r ue 29 dclk_out? da ta clock o utput c o mplemen t 30 dbvdd da ta bus supply v o ltage 31 dbgnd da ta bus supply c o mmon 32 dclk_in+ da ta clock i n put t r ue 33 dclk_in? da ta cloc k i n put c o mpleme n t 34 db7+ da ta bit 7 t r ue 35 db7? da ta bit 7 c o mplemen t 36 db6+ da ta bit 6 t r ue 37 db6? da ta bit 6 c o mplemen t 38 db5+ da ta bit 5 t r ue 39 db5? da ta bit 5 c o mplemen t 40 dbvdd da ta bus supply v o ltage 41 dbgnd da ta bus supply c o mmon 42 db4+ da ta bit 4 t r ue
AD9726 rev. a | page 9 of 24 pin no. mnemonic description 43 db4? data bit 4 complement 44 db3+ data bit 3 true 45 db3? data bit 3 complement 46 db2+ data bit 2 true 47 db2? data bit 2 complement 48 db1+ data bit 1 true 49 db1? data bit 1 complement 50 db0+ data bit 0 true 51 db0? data bit 0 complement 52 dvdd digital supply voltage 53 dgnd digital supply common 54 sdo (syncalrm) spi data output (syncalrm) 2 55 sdio spi data input/output 3 56 sclk (syncupd) spi clock input (syncupd) 4 57 csb spi chip select bar (active low) 58 reset hardware reset (active high) 59 refio internal reference input/output 5 60 fsadj output current full-scale adjust 6 61 sdr_en single data rate mode enable 7 62 advdd analog supply voltage 63 adgnd analog supply common 64 acvdd analog supply voltage 65 acgnd analog supply common pin no. mnemonic description 66 avdd2 analog supply voltage 67 agnd2 analog supply common 68 avdd1 analog supply voltage 69 agnd1 analog supply common 70 ioutb analog current output complement 71 iouta analog current output true 72 agnd1 analog supply common 73 avdd1 analog supply voltage 74 agnd2 analog supply common 75 avdd2 analog supply voltage 76 acgnd analog supply common 77 acvdd analog supply voltage 78 adgnd analog supply common 79 advdd analog supply voltage 80 spi_dis serial port interface disable 8 1 nominally 1 k? to dbgnd (may be omi tted if data clock output is unused). 2 sdo is output in 4-wire spi mode and three-state in 3-wire spi mode. if spi is disabled (spi_dis = advdd), alternate pin function is syncalrm output. 3 sdio is input only in 4-wire spi mode and bidirectional in 3-wire spi mode. 4 if spi is disabled (spi_dis = advdd), alternate pin function is syncupd. 5 bypass with 0.1 f to agnd1. use bu ffer amp to drive external circuitry. limit output current to 1 a. apply external reference to this pin. 6 nominally 2 k? to agnd1 for 20 ma full-scale output (internal reference). 7 if spi is disabled, tie pin to advdd to enable sdr. otherwise, tie to adgnd. 8 tie pin to advdd to disable spi; otherwise, tie to adgnd.
AD9726 rev. a | page 10 of 24 terminology integral nonlinearity (inl) the maximum deviation of the actual analog output from the ideal output, as determined by a straight line drawn from zero scale to full scale. differential nonlinearity (dnl) a measure of the maximum deviation in analog output associated with any single value change in the digital input code relative to an ideal lsb. offset error the deviation of the output current from the ideal zero-scale current. for differential outputs, 0 ma is expected at i outa when all inputs are low, and 0 ma is expected at i outb when all inputs are high. monotonicity a dac is monotonic if the analog output increases or remains constant in response to an increase in the digital input. gain error the deviation of the output current from the ideal full-scale current. actual full-scale output current is determined by subtracting the output when all inputs are low from the output when all inputs are high. output compliance range the range of allowable voltage seen by the analog output of a current output dac. operation beyond the compliance limits may cause output stage saturation and/or breakdown resulting in nonlinear performance. temp er atu re d r i f t temperature drift is specified as the maximum change in a parameter from ambient temperature (25c) to either t min or t max and is typically reported as ppm/c. power supply rejection the maximum change in the full-scale output as all power supplies are varied over their respective operating voltage range. spurious-free dynamic range (sfdr) the difference in decibels between the peak amplitude of a test tone and the peak amplitude of the largest spurious signal over the specified bandwidth. intermodulation distortion (imd) the difference in decibels between the maximum peak amplitude of two test tones and the maximum peak amplitude of the distortion products created from the sum or difference of integer multiples of the test tones. adjacent channel leakage ratio (aclr) the ratio between the measured power of a wideband signal within a channel relative to the measured power in an empty adjacent channel. noise spectral density (nsd) the measured noise power over a 1 hz bandwidth seen at the analog output. total harmonic distortion (thd) the ratio in decibels of the rms power sum of the first six harmonic components to the rms power of the output signal.
AD9726 rev. a | page 11 of 24 typical perf orm ance cha r acte ristics 50 60 70 80 90 100 sfdr (dbc) 04540- 007 0 1 22 4 3 6 4 8 6 07 28 4 9 6 1 3 2 120 108 144 f out (mhz) ?6db 0db ?3db figure 6. sfdr v s . f ou t @ 4 00 m s ps 50 60 70 80 90 100 sfdr (dbc) 04540- 008 01 2 2 4 3 6 4 8 6 0 7 f out (mhz) 2 ?6db 0db ?3db figure 7. sfdr v s . f ou t @ 2 00 m s ps i m d (dbc ) 50 60 80 70 90 100 80 90 1 0 0 120 1 3 0 30 40 50 60 70 20 110 140 f out (mhz) 04540- 009 f1 + f2 = 0db figure 8. tw o-tone imd vs. f ou t @ 400 msp s p o w e r cons ump t i o n (mw ) 550 560 580 570 590 600 620 610 630 100 50 0 150 200 f out (mhz) 04540- 006 sdr ddr figure 9. powe r c o nsumption vs. f ou t @ 40 0 m s ps a 1a p ex t 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?90 ?80 ? 100 ? 120 ? 110 1a vg stop 7.5mhz 675khz start 750khz ref lvl 0dbm 40db dbm rf att unit 1khz 1khz 17s rbw vbw swt 04540- 018 fig u re 1 0 . t h d @ 4 00 m s ps and f ou t = 1 mh z ( d ipl e x e r l o w- pas s out p ut show ing 0 dbm fu nda m ent a l; see pe rfor m a nc e e ffects of ca lib rat i o n sect i o n) a 1a p ex t 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?90 ?80 ? 100 ? 120 ? 110 1a vg stop 7.5mhz 675khz start 750khz ref lvl 0dbm 10db dbm rf att unit 1khz 1khz 17s rbw vbw swt 04540- 019 fig u re 1 1 . t h d @ 4 00 m s ps and f ou t = 1 mh z ( d ipl e x e r h i g h -p as s out p ut show ing ha rm on ics b e f o r e cal i br at io n; see pe rfor m a nc e e ffects of ca lib rat i o n sect i o n)
AD9726 rev. a | page 12 of 24 a 1a p ex t 0 ?10 ?20 ?30 ?40 ?60 ?50 ?70 ?90 ?80 ? 100 ? 120 ? 110 1a v g stop 7.5mhz 675khz start 750khz ref lvl 0dbm 10db dbm rf att unit 1khz 1khz 17s rbw vbw swt 04540- 020 fig u re 1 2 . t h d @ 4 00 m s ps and f ou t = 1 mh z (d ipl e xer h i gh-pass output show ing ha rm on i c s a f ter ca lib rat i on , see pe rfor m a nc e e ffects of ca lib rat i o n sect i o n) 04540-014 span 34.68mhz sweep 1.012s (601 pts) vbw 100khz center 70.00mhz *res bw 10khz rms results carrier power ?14.58dbm/ 3.84000mhz freq offset 5.000mhz 10.00mhz 15.00mhz ref bw 3.840mhz 3.840mhz 3.840mhz dbc ?76.72 ?76.96 ?77.07 dbm ?91.30 ?91.54 ?91.65 lower dbc ?76.69 ?77.04 ?76.76 dbm ?91.27 ?91.62 ?91.34 upper ref ?35dbm *avg log 10db/ pavg 10 w1 s2 *atten 8db ext ref figure 13. on e-carrie r wcdm a @ 40 0 m s ps f ou t = 7 0 m h z 04540-015 span 47.38mhz sweep 1.383s (601 pts) vbw 100khz center 70.00mhz *res bw 10khz 1 ? 20.51dbm 2 ? 20.72dbm total carrier power -17.61dbm/7.68000mhz ref carrier power -20.72dbm/3.84000mhz offset freq 5.000mhz 10.00mhz 15.00mhz integ bw 3.840mhz 3.840mhz 3.840mhz dbc ?70.61 ?71.29 ?71.36 dbm ? 91.34 ? 92.01 ? 92.08 lower rrc filter: on filter alpha 0.22 dbc ? 70.74 ? 71.31 ? 71.06 dbm ?91.47 ?92.03 ?91.78 upper ref ?40dbm *avg log 10db/ p avg 10 w1 s2 *atten 6db ext ref figure 1 4 . t w o-c a r r ie r wcdma @ 40 0 msps f ou t = 7 0 m h z 04540-016 span 59.58mhz sweep 1.739s (601 pts) vbw 100khz center 70.00mhz *res bw 10khz 1 ? 26.43dbm 2 ? 26.53dbm 3 ? 26.74dbm 4 ? 26.88dbm total carrier power -20.62dbm/15.3600mhz ref carrier power -26.43dbm/3.84000mhz offset freq 5.000mhz 10.00mhz 15.00mhz integ bw 3.840mhz 3.840mhz 3.840mhz dbc ?66.59 ?67.63 ?67.59 dbm ? 93.00 ? 94.04 ? 94.00 lower rrc filter: on filter alpha 0.22 dbc ?67.07 ?67.54 ?67.44 dbm ? 93.48 ? 93.95 ? 93.86 upper ref ?45dbm *avg log 10db/ p avg 10 w1 s2 *atten 4db ext ref figure 1 5 . f o ur-c ar rie r wcdma @ 40 0 msps f ou t = 7 0 m h z 04540-017 span 83.98mhz sweep 2.451s (601 pts) vbw 100khz center 70.00mhz *res bw 10khz 1 ? 32.21dbm 2 ? 32.30dbm 3 ? 32.44dbm 4 ? 32.59dbm total carrier power -20.62dbm/15.3600mhz ref carrier power -26.43dbm/3.84000mhz offset freq 5.000mhz 10.00mhz 15.00mhz integ bw 3.840mhz 3.840mhz 3.840mhz dbc ?62.23 ?62.87 ?63.70 dbm ? 94.82 ? 95.46 ? 96.28 lower rrc filter: on filter alpha 0.22 dbc ?62.09 ?62.36 ?62.39 dbm ? 94.68 ? 94.94 ? 94.98 upper ref ?50dbm *avg log 10db/ p avg 10 w1 s2 *atten 2db ext ref figure 1 6 . e i ght-c a rri er wcdma @ 4 0 0 ms ps f ou t = 7 0 m h z
AD9726 rev. a | page 13 of 24 serial port interface table 8. spi register map addr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 sdiodir datadir swreset sleep pwrdwn extref 0x02 datafmt datarate invdclki invdclko disdclko syncman syncupd syncalrm 0x0e calmem[1] calmem[0] calclk[2] calclk[1] calclk[0] 0x0f scalstat selfcal xferstat memxfer smemwr smemrd fmemrd uncal 0x10 memadr[7] memadr[6] memadr[5] memadr[4] memadr[3] memadr[2] memadr[1] memadr[0] 0x11 memdat[5] memdat[4] memdat[3] memdat[2] memdat[1] memdat[0] 0x15 syncout[1] syncout[0] 0x16 syncext syncin[1] syncin[0] table 9. spi register bit defa ult and descriptions values addr name bit i/o default description 0x00 sdiodir 7 i 0 0: sdio is input only (4-wire spi mode), and sdo is used for output. 1: sdio is input/output (3-wire spi mode), and sdo is unused. datadir 6 i 0 0: spi serial data byte is msb first format. 1: spi serial data byte is lsb first format. swreset 5 i 0 1: software reset: spi re gisters (except 0x00) to default values. 1 sleep 4 i 0 1: analog outputs temporarily disabled. pwrdwn 3 i 0 1: full device power-down; all circuits disabled except spi. extref 0 i 0 1: power-down internal re ference: use external reference source. 2 0x02 datafmt 7 i 0 0: input data-word is twos complement binary format. 1: input data-word is unsigned binary format. datarate 6 i 0 0: ddr mode. 1: sdr mode. invdclki 5 i 0 1: inverts polarity of data clock input. invdclko 4 i 0 1: inverts polarity of data clock output. disdclko 3 i 0 1: disables data clock output. syncman 2 i 0 1: enable sync manu al mode; disable automatic update. syncupd 1 i 0 1: force manual sync update. syncalrm 0 o 0 1: indicates that sync logic requires update. 0x0e calmem [5:4] o 00 2-bit smem contents and calibration status indicator. 00: uncalibrated; smem contains default values (63). 01: self-calibrated; smem contains values from self-calibration. 10: factory-calibrated; smem values transferred from fmem. 11: user-calibrated; smem contains user-entered values. calclk [2:0] i 000 3-bit self-calibration clock divider ratio. affe cts time available for algorithm settling. each value increase reduces time by 50%. 3 000: self-calibration clock is dac clock/4096 (maximum self-calibration settling time for highest linearity accuracy). 001,010,011: self-calibration clock is dac clock/2048,1024,512. 100,101,110: self-calibration clock is dac clock/256,128,64. 111: self-calibration clock is dac clock/32 ( minimum self-calibration settling time for fastest algorithm completion). 0x0f scalstat 7 o 0 1: indicates completion of self-calibration cycle. selfcal 6 i 0 1: initiates self-calibration cycle. 4 xferstat 5 o 0 1: indicates completion of memory transfer cycle. memxfer 4 i 0 1: initiates fmem to smem transfer. 5 smemwr 3 i 0 1: enable static memory (smem) write operation. smemrd 2 i 0 1: enable static memory (smem) read operation. fmemrd 1 i 0 1: enable factory memory (fmem) read operation. uncal 0 i 0 1: enable uncalibrated ope ration; all smem to default values. 6 0x10 memadr [7:0] i 00000000 8-bit memory addr ess value for read/write operations.
AD9726 rev. a | page 14 of 24 addr name bit i/o default description 0x11 memdat [5:0] i/o 000000 6-bit memory data value for read/write operations. 0x15 syncout [1:0] o 00 2-bit output value indicates current sync quadrant. syncext 5 i 0 1: enable sync external mode; disable auto quadrant select. 0x16 syncin [4:3] i 00 2-bit input value used to specify sync quadrant. 1 swreset also resets itself. smem contents are unaffected by swreset; however, calmem reports an uncalibrated state. 2 extref is optional because the internal reference circuit is designed to be overdriven by an external source. 3 the self-calibration clock is also used for the memory transfer cycle; therefore, the calclk value affects the memxfer process time. 4 register bits 3:0 must all be 0 to assert selfcal. the t ime required for the self-calibrati on cycle is ~100 ms at 100 mhz with calclk = 0. 5 register bits 3:0 must all be 0 to assert memxfer. the time required for the memory transfer cycle is ~15 ms at 100 mhz with c alclk = 0. 6 the uncal bit remains asserted after the cycle completes (smem co ntents held at default values) until the bit is cleared by th e user.
AD9726 rev. a | page 15 of 24 theor y of opera tion the AD9726 us es l v ds f o r in p u t da t a t o ena b l e hig h s a m p le ra t e s an d hig h p e r f o r ma n c e . l v ds t e chn o log y us es dif f er en t i al sig n als fo r n o is e r e je c t io n and smal l sig n al am p l i t u d e fo r fas t s p eed wi t h lo w e r p o w e r . e a c h l v ds in p u t on t h e AD9726 has a n in t e r n al 100 ? ac ti v e lo ad f o r p r o p er t e r m ina t io n. dac cloc k and da ta clock ou t p ut the AD9726 us es tw o c l o c k in p u ts an d o f f e rs o n e c l o c k o u t p u t . al l a r e dif f er en t i al sig n als. the AD9726 is dr i v en b y a mast er in p u t c l o c k t h a t ini t ia t e s co n- v e rsio n a nd con t r o ls a l l o n -chi p ac t i v i ty . t h is si g n a l is r e fer r e d t o as t h e d a c clo c k. i t is n o t l v ds, an d t h e c l k+ an d c l kC pi ns are h i g h i m p e d a nc e i n put s . the d a c c l o c k is th en us ed t o g e n e ra t e t h e da t a c l o c k o u t p u t . t h e d c lk _o ut + a n d d c l k _o u t C p i n s f o rm a n l v d s sig n al tha t can be us e d t o dr i v e a n ext e r n al fp ga o r a n o t h e r da ta p u m p . i n s d r m o de , t h e da ta c l o c k o u t p u t al wa ys r u n s a t t h e s a m e f r e q uen c y as t h e d a c clo c k. i n d d r m o de , t h e da t a cl o c k ou tp u t a l wa y s r u ns a t ? t h e d a c cl o c k f r e q u e nc y . u s e of t h e d a t a cl o c k output i s opt i on a l . i t i s m e an t to s e r v e a s a c o n v e n i e n t m e a n s o f r e g u l a ti n g th e i n c o m i n g d a t a s t r e a m . the dr i v er ca n b e lo ade d b y a 1 00 ? dif f er en t i a l t e r m ina t io n. an ext e r n al 1 k? r e sis t o r f r o m th e rext p i n to d b gnd is als o r e q u i r e d t o se t th e d r i v e s t r e n g th . i f u n u s e d , th e d a ta c l oc k o u t p ut p i n s ca n b e lef t u n co n n e c te d and t h e 1 k ? r e sisto r a t rext can b e omi t t e d . the da t a clo c k o u t p ut can a l s o b e in ver t e d b y ass e r t in g t h e invd c l k o b i t in s p i reg i s t er 0x02 o r th e dr i v er ca n be d i sa b l e d b y a s ser t i n g th e d i s d c l k o b i t in t h e sa m e r e gis t e r . dat a cloc k in put the r e ma inin g c l o c k sig n al ass o cia t e d wi t h t h e AD9726 is t h e da ta c l o c k in p u t. this l v ds sig n al is n o t o p tional a nd m u s t a c c o m p a n y th e 1 6 - b i t d a ta b u s . t h e d a ta c l oc k i n p u t i s u s ed t o l a tc h i n c o mi ng d a t a i n to t h e s y nch r oni z a t i o n ( s y n c ) l o g i c . t h e d a ta c l oc k i n p u t a l w a y s ru n s a t th e s a m e fr e q u e n c y a s th e d a t a clo c k o u t p u t in b o t h s d r a nd ddr m o de s. a lo g i ca l in versio n can b e acco m p lis h e d b y as s e r t in g t h e invd clki b i t. driving the dac clock inputs the d a c cl o c k m u st b e p r e c is e and sp e c t r a l ly p u re to e n su re t h e hig h est ac p e r f o r ma n c e . a s y mm et r i c a l 50 % d u ty c y cle shou l d b e mai n t a ine d a t a l l t i me s . the cl k+ a nd clkC in p u t p i ns sh o u l d b e dr i v en b y a sig n a l w i t h a c o m m on - m o d e vo lt age ne ar ? of c l k v dd . f r om t h i s p o in t, p e a k - t o - p e a k s i g n a l am pli t u d e sh o u l d swi n g o v er a ra nge o f a t le as t s e v e r a l h u n d r e d mil l i v o l t s. 04540-012 clk+ vcc ? 2v mc100lvep16 vcc = clkvdd = 2.5v vbb = 1.0v 1:1 50 ? 50 ? clk? AD9726 25 ? 25 ? t h e c i rc u i t opt i on s h ow n i n f i g u re 1 7 u s e s a re c e ive r / d r i ve r ic f r o m th e 2.5 v l v p e cl log i c fa mil y t o p r o v ide co m p lem e n t ar y o u t p uts t h a t fal l wi t h i n t h es e gu ide l i n es. a t r a n s f o r m e r h e l p s en sur e a 50 % d u ty c y cle a n d p r o v i d es a si n g le- e nde d to dif f er en t i al con v ersio n a t t h e i n p u t. the l v p e cl de v i ce can b e con v enien t l y p o wer e d f r o m t h e s a m e p o w e r s u ppl y as clkvdd . th e ce n t er t a p o f t h e t r a n s - fo r m er s e co ndar y m u st b e h e l d a t 1 v , t h e sw i t chin g t h r e sh old o f t h e r e cei v er/ d r i v e r in p u ts (u s e a r e sis t i v e div i der t o g e nera t e t h is v o l t a g e o r us e t h e i n t e r n al vbb s o ur ce w i t h a b u f f er a m p l if ier). b a s e d o n a 1:1 im p e dan c e ra tio , 25 ? r e sis t o r s acr o s s t h e s e conda r y p r o v id e a m a t c h e d lo ad t o a 50 ? s o ur ce. the dr i v er o u t p u t s a r e t e r m i n a t e d as clos e as p o s s i b le t o t h e AD9726 wi t h 5 0 ? t o v c c ? 2 v (o r us e a th e v enin eq uivalen t cir c ui t). c o n t r o l l ed im p e dan c e pcb traces sh ou ld be us e d t o mini mi ze r e f l e c t i o n s. sig n a l le vels a t t h e clk+ a nd cl kC p i n s tra n si tio n between a hig h n e a r 1500 mv t o a lo w nea r 750 mv . 0.1 f 0.1 f 04540-013 clk+ vdc bias = 1.25v 1:1 50 ? clk? AD9726 fi gur e 18 . p a ssi ve da c clock drive c i rcuit a n a l te r n a t ive c i rc u i t opt i on f o r d r iv i n g t h e d a c cl o c k i n put s em p l o y s a tra n s m is sio n l i n e tran sfo r m e r (bal un) t o acco m p lish t h e s i n g le -e n d e d t o dif f er en t i al co n v ersio n . thi s al l-p a s s i v e c i rc u i t is c o ns i d e r ably s i m p l e r and l e ss c o st ly , and i t p r ov i d e s accep t ab le p e r f o r ma n c e o v er a limi t e d ra n g e o f f r e q uen c ies. i n t h i s i m pl e m e n t a t i on , a s i ne w a ve ( o r ot he r s i ng l e - e nd e d s o ur ce) is co u p le d dir e c t l y t o t h e dif f er en t i al d a c clo c k i n p u t s thr o ug h a 50 tra n sf o r m e r . ca p a ci t o rs a r e us ed f o r is ola t io n, a nd e a ch d a c clo c k p i n m u st b e dc- b ia s e d to a le vel o f 1.25 v (a p a ir o f sim p le r e sis t i v e di viders ca n be us e d ) .
AD9726 rev. a | page 16 of 24 the 50 ? t e r m i n a t io n r e sist o r sh o u ld b e place d as clos e as p o s- si b l e t o t h e in p u t p i n s , and co n t r o l l e d im p e dance pcb t r aces shou l d b e u s e d . g o o d ac p e r f o r ma n c e can b e e x p e c t e d f r o m ei t h er t h e ac t i v e or p a ss ive d a c cl o c k d r iv e c i rc u i t . h o w e ve r , i n a p a ss ive c i rc u i t , th e o u t p u t s l ew ra t e i s de pen d en t o n t h e f r eq ue n c y o f th e i n p u t; wher eas a n ac tiv e cir c ui t p r o v ides co n s is t e n t l y hig h o u t p u t s l e w ra t e s o v er a wide ra n g e o f in p u t f r eq uen c ies. dat a sy nc hroniza t i o n circui t r y the hig h p e r f o r ma n c e o f the AD9726 r e q u ir es ma in ta inin g sy n c hr o n iz a t io n b e tw e e n t h e i n co min g b i t s an d t h e d a c clo c k us e d t o s a m p le a nd con v er t t h e da t a . d e s p i t e t h e in h e r e n t dif- f i c u l t y in sp e c if yin g t h e phas e re l a t i o n s h i p o f t h e d a c clo c k a nd t h e l v ds da t a clo c k i n p u t a nd t h e chal le ng e p r es en t e d b y th e hig h o p era t in g s p ee d o f t h e in t e r f ace , t h e AD9726 co n t ain s r e a l -t i m e lo g i c to a u to ma t i ca l l y m o n i to r an d a l i g n t h e da t a b u s wi t h t h e d a c cl o c k. w h et h e r i n s d r o r ddr m o d e , in p u t d a t a is a l wa y s p r o v ide d a t t h e s a me ra t e . f u r t h e r m o r e , t h e ra t e o f in comin g da ta al wa ys e q uals t h e f r e q u e n c y p e r i o d o f t h e d a c clo c k. the da t a ra te a n d t h e d a c clock m u st als o b e f r e q uen c y lock e d . t o acco m p lish t h i s , t h e pr i m ar y pu r p o s e of t h e d a t a c l o c k output i s to prov i d e a tim e ba s e f o r d a ta th a t i s d e ri v e d di r e ctl y f r o m th e d a c c l ock . t h e fun c ti o n o f th e da t a c l oc k in p u t i s t o la t c h in co mi n g da ta in t o t h e s y n c b l o c k. f r o m t h er e, i t is t h e f u n c t i o n o f t h e syn c h r o n i z a t i o n logi c t o posi ti o n t h e d a ta wi th r e s p ect t o t h e d a c clo c k fo r o p t i ma l ac p e r f o r ma n c e. i ndivi d u a l da t a b i ts m u st main t a in clos e a l ig n m e n t wi t h on e a n o t h e r so tha t pc b tra c e s h a v e m a t c h e d de la ys a c r o s s th e wi d t h o f t h e 16- b i t b u s. i n ad di t i o n , a f i xe d s e t- u p a nd h o ld ti m i n g r e la ti o n sh i p bet w een t h e da ta c l ock in p u t a n d t h e da ta b u s is r e q u ir e d . h o w e v e r , b e ca use o f t h e syn c l o g i c, t h e p has e r e la t i o n s h i p b e tw e e n t h e d a t a b u s and t h e d a c clo c k is in t e r n a l ly o p t i m i ze d . f u rt h e rm o r e , s h o u l d th e p h a s e b e t w e e n th e d a t a b u s a n d th e d a c clo c k dr if t o v er t i m e o r t e m p era t ur e , t h e syn c log i c a u t - o m a t ic al l y u p da t e s a nd ad j u s t s fo r i t . o n ce sy n c hr o n iza t io n has bee n r e a c h e d , th e p h a s e be t w ee n th e d a ta b u s a n d th e d a c c l oc k c a n v a r y b y a f u l l c y cl e w i t h out l o ss or c o r r upt i on of d a t a . m o re d e t a i l e d e x pl an a t i o ns of s y nc op e r a t i o n a n d opt i on a l p r og ra mma b l e m o des a r e p r es e n t e d i n t h e s y n c l o g i c o p era t ion an d pr og ra mmin g s e c t io n, w h ich a l s o in cl udes an exp l a n a t ion o f ho w t o us e t h e sy n c log i c wi t h o u t th e s p i. analog ou tput the AD9726 is bas e d a r o u nd a hig h d y namic ra n g e cm os co r e . the a n alo g o u t p ut co n s is t s o f dif f er en t i al c u r r en t s o ur ces, ea c h ca pa b l e o f u p t o 2 0 m a ful l sc al e . d i sc r e t e o u t p u t d e vi c e s a r e pmos a nd ca p a b l e o f s o ur c i n g c u r r en t in t o a n o u t p u t t e r m in a t io n w i t h in a co m p l i an c e v o l t a g e ra n g e o f 1 v . i n a ty p i ca l a p pl ica t io n, b o t h o u t p u t s dr i v e dis c rete r e sisto r s-to - an a l o g g r ou nd. f r om t h e r e, e s p e c i a l ly for h i g h e r f r e q u e nc y o u t p u t s, t h ey f e ed t h e cen t er -ta p s e co nda r y o f a 1:1 rf tra n s- fo r m er . a di f f er e n t i al-t o-sin g le-e n d e d co n v ersi o n is acco m p lis h e d t h a t p r o v ide s ad de d ga i n and can c el l a t i o n o f e v en o r der e d ha r m o n ics. 25 ? ?3dbm 25 ? i outa i outb 04540-021 figure 1 9 . t r a n s f or me r output ci rcu i t f o r maxim u m o u t p u t p o w e r , resis t o r val u es can b e in cr eas e d to 50 ? t o p r o v ide u p t o 0 db m in t o a 50 ? lo ad wi t h o u t los s o f p e r f or m a nc e f o r mo st t r ans f or me r s . 04540-011 r ga 50 ? i outa r fa r gb 50 ? i outb r fb notes 1. use rf and rg to set gain and limit bandwidth figure 20. op a m p output circu i t a s an a l t e r n a t i v e, a n ac t i ve o u t p u t st a g e can b e us e d i n t h e classic i n st r u me n t a t io n am plif ie r co nf igura t io n. h e r e , e a ch d a c output f e e d s t h e non i n v e r t i ng i n put of on e of a n a l o g d e v i c e s h i g h sp e e d t r ans i m p e d anc e op a m p s . internal reference and full-scale output the AD9726 con t a i n s a n in t e r n al 1.2 v p r ecisio n r e f e r e n c e s o ur ce; t h is r e fer e n c e v o l t a g e a p p e a r s a t t h e re fi o p i n. i t ca n be us e d t o dr i v e ext e r n al cir c ui t r y if p r o p erl y b u f f er ed . a p pl y a n ext e r n al r e fer e n c e v o l t a g e s o ur ce t o t h e refi o p i n if desir e d . the in ter n al s o ur ce is desig n e d t o be e a sil y o v er dr i v en b y a n ext e r n al s o ur ce; h o w e v e r , t h e in t e r n al r e fer e n c e ca n als o be p o w e r e d do wn usin g t h e e x tref b i t in s p i reg i s t er 0x0 0 .
AD9726 rev. a | page 17 of 24 the r e fer e n c e vol t a g e (ei t her in t e r n al o r ext e r n al) is a p plie d t o a n ext e r n al p r e c isio n r e sis t o r a t t h e fs ad j pin. the r e s u l t ing c u r r en t is in t e r n a l ly a m plif ie d t o p r o v id e t h e f u l l -s ca le c u r r en t a t t h e d a c o u t p u t acco r d in g to th e f o l l o w in g eq ua tio n : i ou t f s = vref / r fsad j 32 t a kin g in t o acc o un t t h e b i na r y val u e a p p e a r i n g a t t h e da t a b u s in p u ts, t h e o u t p u t c u r r en ts i ou t a a nd i ou t b can b e deter m i n e d acco r d in g t o t h e fol l o w in g e q u a t i o n s: i ou t a = i ou t f s d b [15:0]/65536 i ou t b = i ou t f s (1 ? d b [15:0])/6 5536 n o t e t h a t the AD9726 f e a t ur es n o n v ola t ile , fac t o r y-cali b r a t e d ga in usin g t h e i n t e r n a l r e fer e n c e s o ur ce an d a pr e c isio n 2 k? lo ad . ga i n acc u rac y in a n y a p pl ica t io n is, t h er efo r e , dep e nden t up on t h e a c c u r a c y of r fs ad j . reset f o l l o w in g i n i t i a l p o w e r u p an d a p plic a t ion o f a va li d d a c clo c k sig n al , t h e ad9 726 s h o u l d al wa ys be ini t ial i zed wi th an ac tiv e hig h p u ls e o n t h e re s e t p i n. this def a u l ts t h e p r og ra mma b l e r e gi s t e r s , i n i t i a liz e s v o la til e cali b r a t i o n m e m o r y , a n d p r e p a r e s t h e sy n c hr o n iz a t io n lo g i c fo r da t a . t h e da t a b u s sh o u l d b e st a t ic pr i o r to t h e re s e t pu l s e. a f te r re s e t , l v d s d a t a c a n f l ow . the def a u l t st a t e o f t h e ad972 6 is d d r a nd t w os co m p lem e n t b i na r y in p u t da t a . t o us e t h e AD9726 in t h is mo de , i t is n o t n e cess a r y t o p r og ra m a n y device r e g i s t ers. h o w e v e r , t h e s p i is ena b le d b y de fa u l t un less t h e spi_dis p i n is c o nn e c te d h i g h . i f not d i s a bl e d , sp i i n put pi ns s h o u l d no t b e l e f t f l o a t i ng . serial port interface t h e s e ri a l p o rt i n t e r f a c e i s a f l e x i b l e a n d s y n c h r o n o u s s e ri a l co mm un ic a t io ns p o r t a l lo wi n g e a sy in t e r f ac e t o ma n y i n d u st r y st a n d a rd m i c r o c on t r o l l e r and m i c r opro c e ss or proto c o l s (in c l u di n g b o t h m o to r o la s p i? and i n tel? ss r). the i n ter f ac e p r o v ide s r e ad/w r i t e acce s s t o r e g i s t ers t h a t co nf igur e t h e o p era t ion o f the AD9726. the AD9726 s p i s u p p o r ts sin g l e -b yt e an d m u l t ib yt e tra n sf ers as w e l l as ms b- o r ls b- j u st if ie d d a t a fo r m a t s. t h e in t e r f ace ca n b e co nf igur e d in 3 - wir e m o de (i n w h ich s d i o is b i d i r e c t io na l) or t h e def a u l t 4- w i r e m o de (i n w h i c h s d i o and sd o f u n c t i o n as un i d i r ecti o n al da ta i n p u t a n d da ta o u t p u t , r e spe c ti v e l y). communica tion cycle al l co mm uni c a t io n c y cles ha v e tw o phas es. the f i rs t phas e is co n c er n e d w i t h wr i t in g an inst r u c t io n b y t e i n t o t h e spi co n t r o l l er a n d a l wa ys co i n ci des wi t h t h e f i rs t ei g h t r i sin g e d g e s o f sclk. th e ins t r u c t io n b y te pr o v ides t h e co n t r o l l er wi t h info r m a t io n r e g a r d in g t h e s e cond phas e o f t h e c y cle , na m e l y t h e da t a t r a n sfer phas e . i n t h e in s t r u c t io n b y t e , t h e r e a r e t h e n u mb e r of d a t a b y te s to b e t r ans f e r re d ( 1 to 4 ) , a re g i ste r addr ess, and a b i t in i t ia t i n g a r e ad o r wr i t e o p er a t io n. 04540-010 cs b instruction cycle data transfer cycle scl k sdio sdo r/w n1 n0 a4 a3 a2 a1 a0 d7 n d6 n d7 n d6 n d2 0 d1 0 d0 0 d2 0 d1 0 d0 0 fig u re 2 1 . s p i c o m m un ic at io n cy c l e an y co mm unic a t io n c y c l e b e g i n s wi t h cs b g o in g lo w , which als o r e s e ts t h e s p i co n t r o l log i c. s i mi la rl y , an y c o mm unica t io n c y cle en ds w i t h cs b g o in g hig h , w h ich ab o r ts a n y i n com p let e da ta tra n sf e r . on ce a co mm un ica t i o n c y c l e be g i n s , t h e n e xt eig h t scl k r i sin g e d g e s i n t e r p r e t da t a o n t h e sd i o p i n as t h e in st r u c t io n b y t e . instruction by te the ins t r u c t io n b y t e b i t s a r e sho w n i n t h e fol l o w i n g b i t ma p . b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 r/ w n 1 n 0 a 4 a 3 a 2 a 1 a 0 r/ w bi t 7 o f t h e inst r u c t io n b y t e s e le c t s a r e a d o r wr i t e t r a n sfer . i f t h e b i t is s e t hig h , a r e a d o p era t i o n is i n dic a t e d . i f t h e b i t is lo w , a wr i t e op er a t ion is i ndic a te d . n1, n0 bi t 6 an d bi t 5 o f t h e in s t r u c t io n b y t e det e r m in e t h e n u m b er o f d a t a b y te s to b e t r ans f e r re d, a s show n i n t a bl e 1 0 . table 10. n 1 n 0 desc rip t io n 0 0 t r ansf er 1 da ta b y te 0 1 t r ansf er 2 da ta b y tes 1 0 t r ansf er 3 da ta b y tes 1 1 t r ansf er 4 da ta b y tes a4 , a3 , a2 , a1 , a0 b i t 4 thr o ug h bi t 0 o f th e in s t r u c t io n b y t e sp ecif y a 5-b i t b i na r y val u e co r r es p o ndin g t o a va lid reg i s t er addr es s. i n t h e cas e o f m u l t i b yte t r a n sfers, t h e lo ca t i o n s p e c if ie d is ei t h er a n ini t ial o r a co n c l u di n g r e g i s t er addr es s. the s p i con t r o l l er in cr e m e n ts o r de cr em e n ts t h is va l u e to ge ner a te succe s si ve addr ess va l u es dep e ndi n g o n w h et h e r lsb o r ms b j u st if ica t io n is ac t i ve . msb/lsb transfers the s p i ca n su pp o r t b o t h m s b- a nd ls b- j u st if ie d s e r i a l d a t a b y t e f o r m a t s. this f u n c t i o n ali t y is det e r m in e d b y b i t 6 in s p i reg i st er 0x00. t h is b i t def a u l ts l o w , w h ich is msb j u st if i c a t ion. i n th is m o d e , seri al d a ta b i ts a r e w r i t t e n t o a n d/o r r e a d f r o m re g i ste r s s e qu e n t i a l ly f r om bi t 7 to bi t 0 . i f b i t 6 o f s p i reg i s t er 0x00 is s e t hig h , t h e con t r o l l er swi t ch es t o ls b j u st if ica t io n. i n t h is m o d e , d a t a b i ts a r e wr i t t e n t o o r r e ad f r o m r e g i s t ers s e q u en t i al l y f r o m b i t 0 t o b i t 7. w r i t in g t o t h e in st r u c t io n b y t e s is a l s o a f fe c t e d b y t h e ac t i v e j u st if ica t io n.
AD9726 rev. a | page 18 of 24 for multibyte transfers with msb justification, the address in the instruction byte is interpreted as a final address, and its value is decremented automatically by the controller. for multibyte transfers with lsb justification, the address in the instruction byte is interpreted as an initial address, and its value is incremented automatically by the controller. care must be exercised when switching from msb to lsb justification. the controller switches modes immediately once all eight bits of spi register 0x00 are written (even if in the process of a multibyte transfer). for this reason, a single byte command is recommended when changing justification. 3-wire and 4-wire operation bit 7 of spi register 0x00 defaults low, enabling 4-wire spi operation. in this mode, serial data is input from the sdio pin, and serial data is output on the sdo pin. setting bit 7 of spi register 0x00 high enables 3-wi re operation. in this mode, sdio becomes bidirectional and switches automatically from input to output when necessary. the sdo pin in this mode is unused and assumes a high impedance state. as with msb or lsb justification, care must be exercised when switching operational modes. the change occurs immediately once all eight bits of spi register 0x00 are written. writing and reading register data bringing csb low initiates a new communication cycle. the next eight rising edges of sclk latch data from sdio into the instruction byte. if bit 7 of the instruction byte is low, a write operation is enabled. if bit 7 is high, a read operation is enabled. for a write operation, a data byte is latched from the sdio pin into a register on the next eight rising edges of sclk. if the instruction byte bit 6 and bit 5 are not both 0, a multibyte transfer latches data bytes into adjacent registers after each successive set of eight rising sclk edges. depending upon msb or lsb justification, the controller decrements or increments the address value in the instruction byte during the cycle as necessary. if a read operation is enabled, data bits from the register being addressed appear on sdo (or sdio) with each falling edge of sclk. note that for a read operation, the eighth bit of the instruction byte is latched on the eighth rising edge of sclk and the first output bit is enabled on the immediately following falling sclk edge. for multibyte read sequences, the controller adjusts the register address when necessary and subsequent data bit values appear at the output with each falling sclk edge. disabling the spi tie the spi_dis pin high to advdd to disable the serial port interface. in this state, the default ddr operational mode can be changed to sdr by pulling the sdr_en pin high to advdd. in addition, with the spi disabled, the sync logic no longer operates in a fully automatic mode. see the sync logic operation and programming section for a full explanation of sync operational modes. spi pin description the AD9726 spi logic runs from the dbvdd supply rail, and input/output thresholds are based upon a nominal 3.3 v level. the maximum frequency of operation is 15 mhz. chip select (csb) the csb pin is an active low input. it begins and ends any communication cycle and must remain low during the entire cycle. an incomplete cycle is aborted if csb is prematurely returned high . serial clock (sclk) the sclk pin is used to synchronize data to and from the spi registers and the controller state machine runs from this input. it is therefore possible to read and write register data (but not smem/fmem) without a valid dac clock. all input data is registered on the rising edge of sclk and output data bits are enabled on the falling edge of sclk. serial data input/output (sdio) data is always written into the spi on the sdio pin. in 3-wire mode however, data is also driven out using this pin. the switch from input to output occurs automatically between the instruct- ion and data transfer phases of a read operation. in the default 4-wire mode, sdio is unidirectional and input only. serial data output (sdo) serial data is driven out on the sdo pin when the spi is in its default 4-wire mode. in 3-wire mode (or whenever csb is high) sdo is set to a high impedance state. calibration to ensure linearity to the 16-bit level, the AD9726 incorporates 132 calibration dacs (caldacs), which are used to linearize the current output transfer function. each caldac is a 6-bit device and takes its input directly from static memory (smem). there are 127 caldacs associated with each major transition of the 16-bit input data-word (that is, any transition involving the upper 7 msbs). a 128th caldac operates on the sum total of the lower 9 lsbs. the remaining 4 caldacs (129 to 132) are used to adjust the dacs overall transfer function gain.
AD9726 rev. a | page 19 of 24 linearity caldacs operate inversely from their input; that is, as their binary input value increases, the magnitude of their current contribution seen at the AD9726 output decreases. gain caldacs are an exception to this. their contribution seen at the AD9726 output is in direct proportion to their binary input. gain caldacs are also half strength as compared to linearity caldacs, but they are intended to be used together as a unit and thus provide twice the current adjustment range in sum total. calibration memory during production testing, the linearity of the AD9726 is measured and optimized. values for all caldacs are perma- nently stored in nonvolatile factory memory (fmem). at reset, all factory memory contents are transferred to static memory. calmem indicates a factory calibrated state (calmem = 10b). it is also possible at any time to transfer the contents of fmem to smem by asserting the memxfer bit. the xferstat indicator bit then reports the successful completion of the transfer cycle, and memxfer is cleared. note that the memxfer bit (and selfcal) cannot be asserted if any other memory access function is currently enabled (that is, if any bit [3:0] of register 0x0f is high). attempting to assert memxfer (or selfcal) in this case clears any asserted bits in register 0x0f, but the requested cycle does not commence. the factory-to-static memory data transfer cycle requires a number of dac clock cycles. the total depends on the value of calclk. this value sets a divider used to create a slow version of the dac clock, which is intended to extend the settling time available to the self-calibration cycle. however, this divided clock is also used to sequence a memory transfer cycle. the divider is set to its maximum value with calclk at its default value. a memory transfer cycle requires about 15 ms at a dac clock frequency of 100 mhz. this time can be reduced by 50% for every increase in the value of calclk. accessing calibration memory smem or fmem locations can be read at any time by setting the smemrd or fmemrd bit in spi register 0x0f. address and data information can be input and/or output through spi register 0x10 and spi register 0x11, respectively. smem locations can also be written by setting the smemwr bit. register 0x10 and register 0x11 are again used for addresses and data. any time after the smemwr bit has been asserted, the device reports a user-calibrated state (calmem = 11b) until another action changes the calibration memory status. to reset static memory at any time, assert the uncal bit. all smem locations are then reset to their default values (63). calmem reports an uncalibrated state (calmem = 00b). note that uncal remains asserted (and the contents of smem remains at default values) indefinitely. uncal does not clear itself (like swreset) and must be cleared by the user. note also that although spi registers do not depend on the dac clock (they use sclk to sequence the controller state machine), smem and/or fmem access does require a valid dac clock. smem/fmem read/write procedures static and factory memory is accessed through the spi, but it is not part of the spi logic. for this reason, memory access requires a valid dac clock, while spi register access does not. because the AD9726 spi is so flexible, allowing single and multiple byte reads and writes as well as msb or lsb justified data, there are perhaps a number of ways in which a user can access one or more smem or fmem locations. to avoid potential errors, the following procedures for accessing static or factory memory should be followed. these procedures use only single-byte spi commands to ensure the enabling of addresses and the sequencing of memory access. to read from smem or fmem, 1. ensure that bits [3:0] of register 0x0f are clear. 2. begin the sequence by writing the memory address value to register 0x10 with a single-byte spi write command. 3. assert the smemrd or fmemrd bit in register 0x0f with another single-byte spi write command. 4. import the contents of register 0x11 using a single-byte spi read command. 5. clear the smemrd or fmemrd bit with another single- byte command. to wr ite to sm e m, 1. ensure that bits [3:0] of register 0x0f are clear. 2. begin the sequence by writing the data value to register 0x11 using a single-byte spi write command. 3. assert the smemwr bit using a single-byte spi write command. 4. place the memory address value in register 0x10 using a single-byte spi write command. 5. clear the smemwr bit with a fourth single-byte spi write command.
AD9726 rev. a | page 20 of 24 self calibration the AD9726 features an internal self-calibration engine to linearize the transfer function automatically. this can be very useful at temperature extremes where factory calibration no longer applies. the automated cycle can be initiated by asserting the selfcal bit. the self-calibration process calibrates all linearity and gain caldacs based upon a fixed internal reference current. values for all caldacs are stored in volatile static memory. the calstat bit indicates the successful completion of the cycle, and the selfcal bit is cleared. following the cycle, the device reports a self-calibrated state (calmem = 01b). as with memxfer, successful assertion of the selfcal bit requires that bits [3:0] of register 0x0f be clear. if any of these bits are asserted (such that an smem/fmem read/write/clear state is enabled), the self-calibration cycle does not begin. the time required to self-calibrate is dependent on both the dac clock frequency and the value of calclk. because self- calibration requires more time than ordinary operation, the dac clock is divided into a slower version and used to step through the process. time made available to the self-calibration algorithm directly impacts its ability to provide accurate results. a maximum fixed division ratio (4096) corresponds to the minimum default value of calclk (0). the division ratio can be decreased by increasing the value of calclk. each increase in the value of calclk reduces the dac clock division factor (and, therefore, the time made available to self-calibration) by 50%. with calclk at its maximum value (7), the divide ratio declines to its minimum value (32). with calclk at its default value, self-calibration requires approximately 100 ms at a dac clock frequency of 100 mhz. this time can be reduced to under 0.8 ms if calclk = 7. time scales relative to dac clock frequency. performance effects of calibration harmonic distortion for low frequency outputs is primarily a function of dac linearity. figure 10 to figure 12 show the harmonic distortion performance of the AD9726. figure 10 shows a 1 mhz full-scale output tone. the output drives a unique low-pass and high-pass filter called a diplexer. this type of filter presents a uniform 50 load to the dac and splits the output signal into low and high frequency paths. the diplexer's low-pass output passes the 1 mhz fundamental but attenuates higher frequencies, and the diplexer's high-pass out- put passes higher frequencies and attenuates the 1 mhz funda- mental. figure 10 also shows the diplexer's low-pass output. here the noise floor is higher than the harmonic distortion because with a high power input signal, attenuation is required by the spectrum analyzer. figure 11 shows the diplexer's high pass output where the attenuated input signal can be seen. the spectrum analyzer attenuation has also been reduced, which lowers the noise floor. harmonic products at integer multiples of the funda- mental are thus revealed. this is the response using the AD9726 in an uncalibrated state. figure 12 shows a response using the AD9726 in a calibrated state. harmonic distortion due to the nonlinearities of the digital-to-analog conversion have been virtually eliminated. sync logic operation and programming recall that a fixed set-up and hold timing relationship between the data clock input and the data bus must be established and maintained. recall also that the data bus and the dac clock must be frequency locked. because of the sync logic, however, the phase relationship between the data bus and the dac clock is internally optimized. therefore, data arrival propagation delays and concern about data transitions near the sampling instant are eliminated. synchronization is automatically enabled upon reset. once data arrives and synchronization has been achieved, the sync logic continuously monitors itself so that automatic adjustments are made if phase drifts occur over time and/or temperature, automatic adjustments are made. note that the sync function and operation of the sync logic block are transparent, automatic, and ongoing. no programming is required. for applications where it is useful, however, the following programmable control is provided. sync operating states the sync logic can operate in one of three possible modes. the default mode is fully automatic. fully automatic synchronization is accomplished by demulti- plexing the incoming data stream into four channels, each containing every fourth data-word. data-words are present for four dac clock cycles. data is remultiplexed by sampling each channel with the optimum dac clock cycle. initial synchronization is first established through a hardware reset. this also fully enables the synchronization logic to mon- itor and resynchronize, as necessary. the AD9726 resynchro- nizes only if conditions change enough to alter the phase between the data bus and the dac clock by more than one full clock cycle. in this event, an internal alarm occurs and is followed by an automatic update. during resynchronization, two data-words are typically lost or repeated. in addition to fully automatic mode, two semi-automatic modes are available.
AD9726 rev. a | page 21 of 24 sync manual mode in fully automatic mode, the AD9726 both detects when a resynchronization is necessary and initiates an update. in manual mode, automatic updating is disabled. enable manual mode by setting the syncman bit in spi register 0x02. in manual mode, the sync logic still monitors incoming data and the dac clock, but it indicates the need for an update by asserting the syncalrm bit. in this mode, the user is expected to regularly poll the syncalrm bit. when this bit is read back high, the user can issue a manual sync update also by asserting the syncupd bit in spi register 0x02. syncalrm does not indicate that data is being lost but that conditions are close to the point where data may be lost. the sync logic should be resynchronized by asserting syncupd at the next convenient time. in manual mode, users can choose when to update the sync logic. when operating with burst data, issuing a sync update between active bursts updates the system without risking the loss of any data. in fact, because syncupd always forces a resynchronization regardless of operational mode, even users in fully automatic mode can reduce the possibility of data loss by occasionally forcing a sync update during idle activity. if either the data clock or the dac clock is interrupted for any reason, a syncupd should always be executed to ensure that data bus and dac clock phase alignment remains optimized. sync external mode going beyond manual mode, sync external mode offers a greater level of control and can be useful if multiple dac channels are employed in an application. enable sync external mode by asserting the syncext bit in spi register 0x16. manual mode must also be enabled. the four channels into which each incoming data-word is multiplexed are called quadrants. in any mode, the current quadrant value can always be read back via syncout (bits [1:0] of spi register 0x15). at sync update, the logic chooses the optimal quadrant and refreshes the value of syncout. it is also possible to enter a value into syncin (bits [4:3] of spi register 0x16). when external mode is enabled, the logic oper- ates as expected, except that the quadrant value in syncin is used following an update. this can be used to align delays between multiple device outputs. operating with spi disabled if the spi_dis pin is connected high to advdd and the spi is disabled, the sync logic is placed into manual mode. syncalrm status can then be monitored in hardware via the unused spi pin sdo (54), and syncupd requests can be entered in hardware via the unused spi pin sclk (56). if these two pins are connected together, fully automatic sync operation can be achieved.
AD9726 rev. a | page 22 of 24 outline dimensions compliant to jedec standards ms-026-add-hd 0.27 0.22 0.17 1 20 21 40 40 61 80 60 41 14.20 14.00 sq 13.80 12.20 12.00 sq 11.80 0.50 bsc lead pitch 0.75 0.60 0.45 1.20 max 1 20 21 61 80 60 41 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw seating plane 0 min 7 3.5 0 0.15 0.05 view a pin 1 top view (pins down) 6.00 bsc sq bottom view (pins up) exposed pad fig u re 2 2 . 80-l e ad thin p l as t i c qu ad f l at pa ck ag e, e x pos e d p a d [tqf p_e p ] (sv - 80-1) dim e nsio ns sho w n i n mi ll im e t er s ordering guide model t e mper a t ur e r a nge p a ck age descri ption p a ck age o p tion AD9726bsvz 1 ?40c to +85c 80-l e ad t q fp_e p sv -80-1 AD9726bsvzrl 1 ?40c to +85c 80-l e ad t q fp_e p sv -80-1 a d 9 7 2 6 - e b e v alua t i o n boar d 1 z = pb-free part.
AD9726 rev. a | page 23 of 24 notes
AD9726 rev. a | page 24 of 24 notes ? 2005 analo g de v i ces, inc. all rights reserve d . tr adem ar ks and registered tra d emar ks are the prop erty of their respective o w ners . d04540-0-11/05(a)

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